Embedded block coding with optimized truncation (EBCOT) is a key algorithm in JPEG 2000 image compression system. Recently, the bit-plane coder architectures are capable of producing symbols at a higher rate than the capability of the existing MQ arithmetic coders. To solve this problem, a design of a multiple-symbol processor for statistical MQ coder architecture on FPGA is proposed. The proposed architecture takes advantage of simplicity of single-symbol architecture while integrates several techniques in order to increase the coding rate (more than one symbol per clock), reduce critical path, thus accelerate the coding speed. The repeated symbol statistics has been analyzed prior to the proposed architecture using lookahead technique. This allows the proposed architecture to support encoding rate of maximum 8 symbols per clock cycle without stalls and without excessively increasing the hardware cost. This helps to accelerate encoding process, which leads to greatly increase throughput. From the experiments, for lossy wavelet transform, the proposed architecture offers high throughput of at least 233.07 MCxD/S with effectively reducing the number of clock cycles more than 35.51%.
The key algorithm in JPEG2000 image compression system is embedded block coding with optimized truncation (EBCOT). The EBCOT scheme consists of a bit-plane coder coupled with a MQ arithmetic coder. Recently, the bit-plane coding can generate more than one symbol per clock cycle. Consequently, the coding speed is limited and bottlenecked at the interface between the output of the bit-plane coding and the input of the MQ arithmetic coder. Moreover, an efficient designed architecture for MQ arithmetic coder should compromise between processing speed and hardware cost. Therefore, a single symbol processor for arithmetic coder architecture implemented on FPGA is proposed in this paper, since it offers high throughput but requires low hardware cost. The proposed architecture is separated into 2 pipelined stages to break down the whole task into smaller sub-tasks, which leads to great reduction in the critical path. Consequently, it demonstrates no stall, high clock speed and high throughput in the encoding process. These benefits are achieved with the suitable hardware design, pipelining technique, pre-calculation, and prediction process. As a result, the coding speed can be at least 188.99 MHz with the throughput of 188.99 MCxD/S.
